Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi Michael,
May I confirm that the sdc constraint derive_pll_clocks -create_base_clocks solves the initial error (Line 1626)?
For the second error (Line 400), could you open a new forum post so that we can continue the discussion in the new post? This is to avoid confusion to the other user on the error and solution.
For example, Gabriele's error (Line 1613) has different solution and it is tracked in another post: https://forums.intel.com/s/question/0D50P00004eWYpTSAW/tcl-error-in-timing-analysis-phase-using-lvds-serdes-rx-ip
Thanks.
Best regards,
KhaiY