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why not post the code you used....
And what is the "proper count"? the code you origionally posted is a down counter.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dwncounter is
port( clk,rst:in std_logic;
enable:in std_logic;
count:out std_logic_vector(3 downto 0)
);
end dwncounter;
architecture behavioral of dwncounter is
signal counter:std_logic_vector(3 downto 0):="1111"
begin
process(clk,rst)
begin
if (rst='1') then
counter<=(others=>'0');
elsif rising_edge(clk) then
if(enable='1'and counter/="0000") then
counter<=counter-1;
end if;
end if;
end process;
count<=counter;
end behavioral;
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