Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

task-to stop counter when it reaches "0000"

4 bit down counter

...

...

architecture behavioral of dwncounter is

signal counter<= std_logic_vector(3 downto 0);

begin

process(clk, rst)

begin

if (rst='1') then

counter<="0000";

elsif rising_edge(clk) then

if(enable='1') then

counter<=counter-1;

end if;

end if

the task is to stop counter when it reaches "0000" i.e; the signal sholud go low even if the enable signal is high. plzz help...

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Why not simply replacing:

    if(enable='1')

    with:

    if (enable='1') and (counter /= "0000") ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    How about posting your first attempt, and tell us whats wrong...

    --- Quote End ---

    after the code is compiled when i go for simulation i set the end time as 400ns.. at the rising edge when enable is high the counter starts counting. then when it reaches 0000 it again gets loaded with 1111 and starts counting again.. i dont want the counter to count again even if enable is high..
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    hii did it.. after simulation the counts appear like this... " F E C D C A B A 8 9 8 6 7 6 4 5 4 2 3 2 0 1 0"

    I hve set the end time as 400 ns and start is 0 ps..

    wt to do to get proper count..? plzz help
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Why not simply replacing:

    if(enable='1')

    with:

    if (enable='1') and (counter /= "0000") ?

    --- Quote End ---

    hii did it.. after simulation the counts appear like this... " F E C D C A B A 8 9 8 6 7 6 4 5 4 2 3 2 0 1 0"

    I hve set the end time as 400 ns and start is 0 ps..

    wt to do to get proper count..? plzz help
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    why not post the code you used....

    And what is the "proper count"? the code you origionally posted is a down counter.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    And what is the "proper count"? the code you origionally posted is a down counter.

    --- Quote End ---

    I guess he refers to the glitches (or whatever they are) he obtains in the counter every time he has a 1 to 0 transition on bit 0.

    @Naeem

    add this: signal counter_out<= std_logic_vector(3 downto 0);

    and assign: counter_out <= counter;

    This way counter_out should display the proper count
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    why not post the code you used....

    And what is the "proper count"? the code you origionally posted is a down counter.

    --- Quote End ---

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_unsigned.all;

    entity dwncounter is

    port( clk,rst:in std_logic;

    enable:in std_logic;

    count:out std_logic_vector(3 downto 0)

    );

    end dwncounter;

    architecture behavioral of dwncounter is

    signal counter:std_logic_vector(3 downto 0):="1111"

    begin

    process(clk,rst)

    begin

    if (rst='1') then

    counter<=(others=>'0');

    elsif rising_edge(clk) then

    if(enable='1'and counter/="0000") then

    counter<=counter-1;

    end if;

    end if;

    end process;

    count<=counter;

    end behavioral;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Your code shows a down counter that only counts when enable is high and counter is not 0.

    What about a testbench?

    where does the clk come from?

    shouldnt you be resetting counter to "1111" rather than "0000"?