Sytem Verilog one-hot selection

It is true that Modelsim 6.2 doesn't support "unique". You can't help it if you use features unsupported by the tools. Possibly (hopefully) Modelsim 6.3 does. At least it mentions additional SV support.

A simulator supporting the "unique" keyword would, at the very least, give a run-time warning. This alone by itself is much more than using the synthesis full_case attribute, which will be completely ignored by the simulator.

And the value assigned would be 'x', if you wouldn't have included the (o = d) assignment previous to the case statement. You included it because otherwise Quartus would infer a latch, which is forbidden by the always_comb block. But if Quartus would fully support "unique" as per the standard, it would infer a full case, and then no previous assignment would be needed.

So this means that the keyword does change the semantics under simulation. At least at the extent of assigning X, and not the previous value.

I don't see this as a language flaw. I agree that the "unique" word might be a bit misleading. But this is not the only case in Verilog (and almost every language has some of those), and I wouldn't qualify this as a flaw.