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Altera_Forum
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8 years ago

SystemVerilog error: parameter with complex/aggregate value must have a type

Hi, everyone. I am the first time asking the questions here. I want to declare a double array parameter. However, I meet an error as below. Can someone help me? Thank you very much. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank you very much. I try it.

However, I meet another error.

Error (10161): Verilog HDL error at command_lookup.v(87): object "bit" is not declared. Verify the object name is correct. If the name is correct, declare the object.

Do you know what it is?