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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Please - try modelsim. It will REALLY help you debug your code.

Trying to debug at the gate level is really not going to help here.

The synthesisor is only doing what you've told it. There is likely a bug in your Verilog, that I dont have time to look at. This should be your job.

My review - the code is still overly complicated. All you need is a counter in S5. The counter counts while you're in S5, then when you reach the correct value, you move to S6.