Honored Contributor
Honored ContributorHi Tricky,
Thanks for the tip, I did the change based on your suggestion and the code seems now cleanest, but the function next_state isn´t still working as expected, and I presume that compiler is creating extra registers which could avoid the proper functioning. I´m putting bellow the last version of the code, and also attached the .vcd testbench generated by Simulation Waveform editor of QuartusII. Just to review the need: The basic idea is to create of a function that once called, increments a sub-state at each clock event, and keep itself in the main state while not reached the last sub-state; on other words, it´s a kind of run sub states at a bottom layer. Can you see something clearly wrong on this program regarding to the fundamentals of coding on Verilog/SV ?parameter ST_SIZE = 4 ;
parameter ST_START = 4'b0 ;
parameter ST_STEP = 4'b1 ;
module moore_mac
(
input clk, data_in, reset,
output reg data_out
);
//******************************* Parameter definitions
parameter S0 = ST_START ;
parameter S1 = S0 + ST_STEP ;
parameter S2 = S1 + ST_STEP ;
parameter S3 = S2 + ST_STEP ;
parameter S4 = S3 + ST_STEP ;
parameter S5 = S4 + ST_STEP ;
parameter S6 = S5 + ST_STEP ;
parameter S7 = S6 + ST_STEP ;
parameter S8 = S7 + ST_STEP ;
parameter S9 = S8 + ST_STEP ;
parameter S5_3 = ST_START ;
parameter S5_2 = S5_3 + ST_STEP ;
parameter S5_1 = S5_2 + ST_STEP ;
parameter S5_0 = S5_1 + ST_STEP ;
//******************************* Type declarations
typedef struct packed {
logic Level_main ; // Current state ( main level )
logic Level_sub ; // Target sub-state ( 1 depth bellow )
logic Level_subcurr ; // Current sub-state ( 1 depth bellow )
} FSM ;
//******************************* Varable declarations
reg res = 0 ;
reg ires = 0 ;
FSM StateMachine ;
//********************************** Determine the next state
always @ ( posedge clk )
begin
ires <= reset ;
res <= ires ;
end
always @ ( posedge clk or posedge res )
begin
if (res)
begin
StateMachine.Level_main <= S0 ;
end
else
begin
case (StateMachine.Level_main)
S0:
StateMachine.Level_main <= S1;
S1:
if (data_in) StateMachine.Level_main <= S1;
else StateMachine.Level_main <= S2;
S2:
if (data_in) StateMachine.Level_main <= S1;
else StateMachine.Level_main <= S3;
S3:
StateMachine.Level_main <= S4;
S4:
begin
StateMachine.Level_main <= S5;
StateMachine.Level_sub <= S5_0;
StateMachine.Level_subcurr <= S5_3;
end
S5:
StateMachine <= next_state (
StateMachine.Level_main ,
StateMachine.Level_sub ,
StateMachine.Level_subcurr
) ;
S6:
StateMachine.Level_main <= S7;
S7:
StateMachine.Level_main <= S8;
S8:
StateMachine.Level_main <= S9;
S9:
StateMachine.Level_main <= S0;
default:
StateMachine.Level_main <= S0;
endcase
end
end
//********************************** Determine the output value
always @ ( posedge clk )
begin
case ( StateMachine.Level_main )
S0:
data_out <= S0 ;
S1:
data_out <= S1 ;
S2:
data_out <= S2 ;
S3:
data_out <= S3 ;
S4:
data_out <= S4 ;
S5:
data_out <= S5 ;
S6:
data_out <= S6 ;
S7:
data_out <= S7 ;
S8:
data_out <= S8 ;
S9:
data_out <= S9 ;
default:
data_out <= S0 ;
endcase
end
// *********************************************************************
// Increments sub-state and get out to next main state after completion
// *********************************************************************
function FSM next_state(
input logic valStateBefore ,
input logic valSubstateBefore ,
input logic valSubstateCurrent
);
FSM next_state_return ;
if ( valSubstateCurrent < valSubstateBefore ) // increments sub-state, but keep main state unchanged
begin
next_state_return.Level_main = valStateBefore ;
next_state_return.Level_sub = valSubstateBefore ;
next_state_return.Level_subcurr = valSubstateCurrent + ST_STEP ;
end
else // increments main state
begin
next_state_return.Level_main = valStateBefore + ST_STEP ;
next_state_return.Level_sub = valSubstateBefore ;
next_state_return.Level_subcurr = valSubstateCurrent ;
end
return next_state_return ;
endfunction
endmodule
