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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Fine, I´m currently downloading the Modelsim pack, but I confess that I didn't understand something: You said before on post# 7 that these unused states were removed during synthesis, but if Modelsim acts on scope of simulation which occurs sequentially after, how would both variables would be viewable if were supposedly removed ?