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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
Altera_Forum's avatar
Altera_Forum
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11 years ago

If you did an rtl simulation, with an rtl simulator (like modelsim that you can get for free with quartus) then you would see all of your variable work as you intended.

The quartus simulator is very limited.