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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Ok I got, but I´m not sure if this feature is useful during developing.

There is some way for me to "force" such a synthesis ?

Sometimes is quite useful perform simple constructs and simple simulations whose structure will be further improved.