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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
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Altera_Forum
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11 years ago

Hi Tricky,

I´m using default simulator from QuartusII; in other words, I didn´t configured anyone, leaving as <NONE>, according to page 7 of this (ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_quartus_intro_verilog.pdf) tutorial, and the input signals are being generated directly on Waveform Editor. The file that contains the project files are attached, and output picture bellow.

Please note that the whole design are working, except the above mentioned variables ( optimized as constants, as you said ) which are read on simulation as "0" value, wherever I place the cursor.

http://www.alteraforum.com/forum/attachment.php?attachmentid=10190&stc=1