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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
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Altera_Forum
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11 years ago

There are no registers described here. CurrentState is a variable that is being set at reset, and then never changing again. So the synthesisor will just assign them as constants.

Level_main and level_sub both initialise to 3'b0. At reset level_sub should be getting set to 3'b100

What exactly is going wrong? in a synthesised system this variable would just dissapear as it has no effect on any output.