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Altera_Forum
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11 years ago

System Verilog: Can´t change value of a "struct" variable

Hi, I´m newbie on Verilog, actually also in System Verilog, but worked long time ago with VHDL and C++ languages. I used a template of a Moore state machine from ALTERA for Verilog, and pe...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks Trcky, but after reset state, the registers wouldn´t not keep these values ?

I mean, if I understood correctly, the code bellow stores some values that will remain after reset, or I´m wrong ? 

if (reset)
                begin 
                    CurrentState.Level_main <= S0   ;
                    CurrentState.Level_sub  <= S3_0 ;                    
                end

If not, is there any way to do this in the synthesis?