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Altera_Forum's avatar
Altera_Forum
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15 years ago

synthsis problem

Hi , for a university project I programed ( VHDL) some program to test FPGA errors under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU...
Altera_Forum's avatar
Altera_Forum
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15 years ago

ok , I used ALTPLL megafunction to create 2 clocks for my design, still the same result... it uses the pll but still no use of any logic...