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Altera_Forum's avatar
Altera_Forum
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15 years ago

synthsis problem

Hi , for a university project I programed ( VHDL) some program to test FPGA errors under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I suspect that the way you are using the variables means that it thinks it doesnt need the value from clock cycle to clock cycle, meaning random_num is always '0'. Or it could be because you have the random_num output outside of the clock.

Either way, I would use signals instead of variables.

but for a first attempt, try re-arranging the code like this: 


process(clk)
   variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 =>  '1',others => '0');
   variable temp : std_logic := '0';
begin
   if(rising_edge(clk)) then
     random_num <= rand_temp;
    temp := rand_temp(width-1) xor rand_temp(width-2);
    rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
    rand_temp(0) := temp;
  end if;
end process;