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Hi ,
for a university project I programed ( VHDL) some program to test FPGA errors
under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU *2----> comparator to compare the results from the 2 ALU'2---> the output is one bit error when the results are not the same.
when I compile it in QUARTUS I see in the compilation report that the device only use the pins and no logic/LUT or anything else is being used.
do you have any idea why? / how to fix it?
thanks ...
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Hi,
without seeing the source code it is difficult to say. The synthesis tool has removed your logic. This could happen e.g no output depends on the inputs, the clk is not connected,
a reset is not connected ......
Kind regards
GPK
Honored Contributor
