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Altera_Forum
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14 years ago

Synthezing Designware elements using Quartus II

Hello,

I am trying to map an old design to FPGA. This design contains some designware (DW02_add, DW_02_mult, DW02_tree, etc) elements which were originally included to allow the device to meet timing on an older version of the DC compiler toolset.

Is it possible to allow synthesize these elements using quartus II? Is there any synthesis related settings I should look at configuring?

- Vinnie

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Sorry, just in case I didn't have enough information about the device and version of quartus I am using.

    The device I am using is a stratix II device: EP2S180F1020C3

    The version of quartus I am using is: 9.1

    If anyone has had any experience with this I'd appreciate their insight.

    - Vinnie
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    Altera_Forum
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    Hi thepancake,

    Thanks for the response. Reading that thread doesn't look too promising. I will have to try investigate it further.

    - Vinnie
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    Altera_Forum
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    --- Quote Start ---

    Hi thepancake,

    Thanks for the response. Reading that thread doesn't look too promising. I will have to try investigate it further.

    - Vinnie

    --- Quote End ---

    Hi,

    as far as I know there is still no direct synhtesis support for DW elements in Quartus implemented. All the hints in the Quartus help describe a flow where you have to use "Design Compiler" ( that's the synthesis tool of Synopsys).

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Hi,

    as far as I know there is still no direct synhtesis support for DW elements in Quartus implemented. All the hints in the Quartus help describe a flow where you have to use "Design Compiler" ( that's the synthesis tool of Synopsys).

    Kind regards

    GPK

    --- Quote End ---

    Hi GPK,

    Thanks again for the response. There doesn't seem to be much information online on this subject (Anything I could find, you seemed to be involved in the discussion :)).

    I decided to have a look at our ASIC synthesis setup and it seems we have a library of these elements included as part of our companies greater CAD library. Up until now all simulations I had run used simulation only models. I have included these as part of my fpga project and the whole design seems to have come through synthesis.

    If the final design will actually work on fpga is another thing. I will update you if I manage to get this working! It seems like I'm not the only person who encountered this.

    - Vinnie
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Hi GPK,

    Thanks again for the response. There doesn't seem to be much information online on this subject (Anything I could find, you seemed to be involved in the discussion :)).

    I decided to have a look at our ASIC synthesis setup and it seems we have a library of these elements included as part of our companies greater CAD library. Up until now all simulations I had run used simulation only models. I have included these as part of my fpga project and the whole design seems to have come through synthesis.

    If the final design will actually work on fpga is another thing. I will update you if I manage to get this working! It seems like I'm not the only person who encountered this.

    - Vinnie

    --- Quote End ---

    Hi,

    you should also have a look to SynplifyPro or Certify from Synopsys, because that are FPGA synthesis tools. Maybe the FPGA synthesis tool from Mentor ( I don't know the name at the moment) also supports the DW elements.

    Kind regards

    GPK