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llpo's avatar
llpo
Icon for New Contributor rankNew Contributor
2 years ago

Synthesize NIOS II with different .qsf and no time_limited

Hi, We are 100% new to Quartus (and FPGA in general). I have a project (the DE1-SoC Computer System that comes by default with the University Program when using NIOS II), that I would like only to...
KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Greetings and welcome to Intel's forum.

May I know the Quartus version(17.0 or 19.1 etc) you are using? And May I confirm with you the DE1 soc you are using is a Cyclone V with ARM SoC core?


When using the Quartus Prime Web Edition, compiling a design with a Nios II/s or Nios II/f processor will produce a time-limited SOF file. As a result, the board must remain connected to the host computer, and the design cannot be set as the default configuration. Designs using only Nios II/e processors and designs compiled using the Quartus Prime Subscription Edition do not have this restriction.


You may need to request a paid license to use the Quartus Prime STANDARD version and using the Nios II/e core to avoid the time_limited part.


I have here a manual on more information of the DE1-soc Computer for your reference: https://ftp.intel.com/Public/Pub/fpgaup/pub/Intel_Material/18.1/Computer_Systems/DE1-SoC/DE1-SoC_Computer_NiosII.pdf


Hope to hear on your feedback and looking forward to your feedback.


Thank you.

Regards,

Kelly