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Honored Contributor
Honored ContributorSynthesize multipliers on distributed logic?
Hello, I want to synthesize a symmetric FIR filter with 116 taps. Thus, the design should infer 58 multipliers. As I start the design flow for a Cyclone V (5CSEMA4U23C6) with 84 DSP blocks, everyt...
Altera_ForumHonored Contributor
Honored ContributorMy little exercise is completed. The symmetric 116 tap FIR filter (18 bit coefficients) fits into the small Cyclone V FPGA with 25 DSP blocks. That means, the tool can even place the multipliers on distributed logic. This can be achieved by the multstyle synthesis attribute. Thanks for the help.
