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Honored Contributor
Honored ContributorSynthesize multipliers on distributed logic?
Hello, I want to synthesize a symmetric FIR filter with 116 taps. Thus, the design should infer 58 multipliers. As I start the design flow for a Cyclone V (5CSEMA4U23C6) with 84 DSP blocks, everyt...
Altera_ForumHonored Contributor
Honored Contributoryou can individually control each multiplier using the multstyle synthesis attribute:
http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_multstyle.htm
