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Just a pity that it is not explicitly defined, but must be discovered by trials and errors.
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It is difficult to define exactly what is and what isnt supported. VHDL is a behavioral language. The synthesisor tries to translate the bahaviour into gates and registers (and memories, tri-states, etc). Plus the fact different chip families have different architectures, so the same code will map to different things on different chips.
The best you can get is the chapter I mentioned - it is the best place on how to learn how to write good, re-usable VHDL. Plus the IEEE std 1076.6 outlines the basic structure for synthesisable VHDL code, which is taught in many text books and tutorials (even by altera itself).
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