There is no synthesisable "subset" of any HDL. HDL stands for "hardware description language". So you are just discribing a circuit behaviour. Then the tools try and understand your code to translate it into hardware. The thing is, the tools generally get better with each version as to what code they can translate into real hardware.
Altera does provide a chapter in the Quartus handbook, entitled "Recommended HDL coding styles" (
http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf) which descibe how you should write your behavioural code to get the synthesisor to translate it into the basic elements of the chip. This chapter has been included in the handbook for as long as I have been coding VHDL (8+ years).