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Altera_Forum
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12 years ago

synthesizable VHDL subset

Call me an idealistic noob, but it does not seems that Altera provides any description of the VHDL subset which can be synthesizable by its tools, and this bothers me a lot. Still pass the VHDL...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Not really, ted...

Those documents only describe which parts of the IEEE Standard VHDL Language Reference Manuals are supported by the Quartus tools. But these language reference manuals define only simulation semantics of the language.

I would like a synthesis semantics for the Altera tools. I am looking for a kind of "IEEE 1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis" for VHDL 2008 as implemented by Altera. A little bit like http://gcc.gnu.org/onlinedocs/gnat_rm/implementation-defined-characteristics.html#implementation-defined-characteristics, defining how a given compiler implements the Ada language definition...