Synthesis tool optimizing out block?

Quartus II and Design Compiler are implementing different optimization flows. You don't need a "uniquify" command in Quartus II - the compiler already creates unique netlists for each instance and optimizes them using their appropriate context in the design, e.g. some inputs tied to constants. What you don't like is the way Quartus II merges duplicate logic from unique hierarchies, which can be disabled by assignment. If you want to embed the assignment in HDL, use altera_attribute

(* altera_attribute = "-name REMOVE_DUPLICATE_LOGIC off" *) module m(...);

or in your entity

library altera;

use altera.altera_syn_attributes.all;

entity E is

generic (...);

port (...);

attribute altera_attribute of E : entity is "-name REMOVE_DUPLICATE_LOGIC off";

end entity E;

Also, REMOVE_DUPLICATE_LOGIC preserves duplicate logic cones AND duplicate registers. REMOVE_REDUNDANT_LOGIC_CELLS only protects duplicate LCELL buffers and WYSIWYGs, i.e. it doesn't protect duplicate logic cones that don't feed an LCELL buffer.

Why are you concerned about duplicate logic extraction? Timing? If you simply want to make assignments to registers in the duplicate hierarchy, go ahead and do so. If two duplicate registers have different assignments, the synthesis engine won't merge them.