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I discovered this soon after I placed the last post. In addition to Remove Duplicate Registers - OFF, I also set Remove Redundant Logic Cells - OFF. After I did this, and then reran the compilation, the synthesis tool reported it was elaborating the instance that was being removed. So this command definitely worked.
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Just to be clear, Quartus II does not elaborate (generate an initial netlist from the HDL) every single instance in the design. If two instances are instantiating the same entity + parameter/generic overrides and the two instances don't differ in any assignments that might affect elaboration, you'll only see one message such as,
elaborating entity "foo" for hierarchy foo:inst". . Later, the compiler will replicate the netlist for the duplicate hierarchies when it starts stitching together the final netlist for the design. It doesn't duplicate extract at the level of user instances - it only identifies duplicate gates, mxes, operators, registers, etc and those algorithms run mostly on the flat netlist.
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