Synthesis tool optimizing out block?

report_clocks does not list unconstrained clocks.

The Fitter needs the clocks constrained the same way that final timing analysis does; the .sdc that works for TimeQuest works for the Fitter too. My point with my example where the LUT name is used in the Fitter report and the register name is used in the TimeQuest reports is that the Fitter report will let you find out about that LUT-driven clock that is generally a discouraged design practice for FPGAs. Even after you constrain the clock at the point of the register in the clock path, you would never know from just the TimeQuest reports that there was a LUT in the clock path after that register unless you happened to use report_timing to look at the clock detail in a path using that clock.