Synthesis switch for .sdc ?

SDC files are in fact Tcl code, so you can use standard Tcl programming to put decisions in your code. You have to be careful though because TimeQuest doesn't not digest all statements well, e.g. the 'post_message' will upset the synthesiser and prevent it from doing 'timing driven synthesis'.

set family "Cyclone II"
...
if {$family == "Cyclone II"} {
	set pllclk0 "pll|altpll_component|pll|clk"
	set pllclk1 "pll|altpll_component|pll|clk"
	set pllclk2 "pll|altpll_component|pll|clk"
} else {
	if {$family == "Cyclone IV E"} {
		set pllclk0 "pll|altpll_component|auto_generated|pll1|clk"
		set pllclk1 "pll|altpll_component|auto_generated|pll1|clk"
		set pllclk2 "pll|altpll_component|auto_generated|pll1|clk"
	}
}
...
set_input_delay -clock $pllclk0 -max 1.5 Writing

I too share your concern for zero-warnings (I wish Altera's IP-designers would too), as "a warning is an error waiting to happen". I heard this quote over 20 years a go, in a discussion over the then at-that-time very 'loose' C-programming