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Altera_Forum
Honored Contributor
Honored ContributorSynthesis support for SystemVerilog files in Quartus Prime Version 16.0.0
Hi all, I am trying to synthesize a SystemVerilog (.sv) file in Quartus Prime Version 16.0.0. I get the following error while using "for" statements without the explicit "generate" stateme...
Altera_ForumHonored Contributor
Honored ContributorI get the feeling it is not supported. See here for a list of what SV features are supported:
http://quartushelp.altera.com/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm
