Synthesis output for multiple driver within one always

I see.

However, I am not completely clear on this.

My understanding of multiple drivers is this:

You have a flop. Two signals are driving the input of the flop at the same time - Which cannot be possible.

Now, in this code. considering two scenarios by itself.

a<= 1; is an unconditional non-blocking statement. This takes place every clock cycle.

On the hardware I believe this to be a gnded wire connected to the D input of the flop.

if(x==1) a<=0; This would be a mux whose output is driving the input of the D flip flop.

Looking at the above two conditions, when x equals one. We have two wires with different values driving the input of the flop. Could you please tell me how different this is from a multiple driver?

Although this would make sense if

always@(posedge clk)

begin

a<= 1;

if(x==1)

a <= 0;

end

is same as

always@(posedge clk)

begin

if(x==1)

a<=0;

else

a<= 1;

end

Your help is appreciated. Thanks