Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Synthesis output for multiple driver within one always

Hi, I came across a code snippet and has been boggling my mind quite a bit. The equivalent to the code is below: a is output and x is an internal register always@(posedge clk) begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

No, it is not. a will be as simulation - it will be 0 when x = 1 and 1 when x = 0

This is just a registered inverter.

A single always block can always be condensed into logic (and registers if it is a synchronous process). For any given event, there is a single output.

You only get multiple drivers with more than 1 always blocks or assignments as multiple events cause multiple drivers on the same signal.