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Hi all,
I need some clarification that I don't understand by quartus II documentation.
I have to port on EP4SE530H35C2S a quite big device,
to load withouth partitions it takes several days for elaboration and synthesis.
I am going to partition the design,
I put some empty modules for the partitions and I want synthetize in separate projects them.
For me,
it's not clear the flow, because after load the HDL files I don't
have the hierarchies to put partitions.
To put the partions settings, do I need "Analysis & elaboration"
then I see the hierarchies?
In this case to execute "Analysis & elaborations"
it takes long time (13 hours) also with "fast compilation" setting.
If I write a tcl scripts, to partiton the design, before "Analysis & elaboration", is it enough the setting the partitions by:
set_global_assignment -name PARTITION_NETLIST_TYPE EMPTY -section_id "<module_name>:<cell_name>" ?
If I write the TCL script by quartus after put the "partitions" by quartus/gui,
in the generated script i see, apart previous command:
set_instance_assignment -name PARTITION_HIERARCHY <cell_name>_<strange_number> -to "<module_name>:<cell_name>" -section_id "<module_name>:<cell_name>"
Do I have to put this command in my script or it is enough only the command:
set_global_assignment -name PARTITION_NETLIST_TYPE EMPTY -section_id "<module_name>:<cell_name>" ?
How can I get the number "<cell_name>_<strange_number>" in previous command.
I hope it's clear.
Regards
Zancaro
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Hi,
before you start with design partitions you should look why your "Analysis & elaborations" takes so long. I also have projects with large StratixIV FPGA's and I never had such long runtimes.
In order to get the hierarchy I would define a blackbox for each design part which should be handled as partition.
Kind regards
GPK
Honored Contributor
