synthesis error 10818

Here is an update - although this workaround worked well for the pruned test case, it also works for the "real" code:

always @(posedge clk or posedge rst )
begin
   new_bw <=0;  
  
  if (rst) begin
    m_wr_pnt<=0;
    
    write_cnt<=0;
    new_bw <=0; 
   
  end
  else if (we_m) begin    
    if (free_bd >0) begin
      write_cnt <=~ write_cnt;
      m_wr_pnt<=m_wr_pnt+1;
      if (!write_cnt) begin  //First write indicate source buffer addr
        bd_mem<=dat_in_m;            
      end
      else begin        //Second write indicate SD card block addr
        bd_mem<=dat_in_m;
        new_bw <=1;     
      end
     end
  end   
       
end

but the issue now is - moving new_bw to an 'else' clause requires putting it there several times. It's far from mechanical patch. The pattern of

always ... begin 
xyz<=0; 
if ... if ..  if .. then xyz <=1  ... 
end

is rather frequent in the sdc_controller code.

So, although this is a workaround, the resulting code is difficult to understand and VERY prone to errors - if you miss one branch, you'll get a register that holds value longer then 1 clock cycle, which is not what is intended.

I still wonder if there is option or way to make Quartus understand this rather simple preposition - a default value on the signal in the always block.

So, what about simply removing 'rst' from the always sensitivity list? This is not quite the same function, but if reset is simply a reset there, not cigar pretending to be a reset :-) it may work.