syntax errors.

The hardest thing about learning any HDL is learning to think in non-sequential terms. You seem to be seeing your imem component as a function call. Each entity in your VHDL describes a piece of hardware that operates concurrently with all the other hardware components. Just instantiate the component outside the process. Yes, it means that you will always fetch from the instruction memory on every clock edge. By fetch, I mean, you will always read from the memory. So what? What matters is when you use the memory outputs q_a and q_b and update the program counters. You're state machine controls this behavior.