Synplicity run time issue

I think I missed something with your post. Is it Synplify run times or Quartus run times? Your post starts off saying Synplicity but the Virtual Pins are all done in Quartus after the Synplify runs. Are you running PERIPHERY once as a separate Synplify project and writiing out a .vqm, then running CORE as another project, and then adding them together in Quartus. If this is causing Synplify run times to go up, I really have no idea, as they have a pretty straightforward task that tends to be linear with design size.

In Quartus, I'm not sure why you're doing Virtual Pins. They tend to be used when fitting just a sub-section of the design by itself, and it has more I/O than the device actually has available. So for the most part they're not used when targeting real hardware. That being said, you may be using them if doing a bottom-up Incremental Flow(most people using Incremental Compilation aren't doing the bottom-up flow, so I'm just checking). In that case you're actually placing and routing PERIPHERY and CORE in separate projects(or maybe just PERIPHERY and then importing that place and route information into the CORE project). If this is the case, are you using LogicLock regions? Also, what device and approximately how full is it? And which part causes the 2x to 4x increase, is it the fitter? If it is, there are messages that say how much time was spent placing, how much routing, etc., so it might be worthwhile to check which part is increasing.