Synchronization problem

Hi,

I have a design that is transferring multiple data bits from slower clock domain to faster clock domain.

The problem that I'm facing is that whilst the design runs nicely on fpga (no synchronization errors) the design assistant keeps bugging me with this warning:

"Warning: (Medium) Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain."

I've used mux recirculation scheme to synchronize the data bits.

So my question is as follows : Should I ignore this message or should I try to to describe syncrhozation scheme with different VHDL code syntax?

I've read the Altera documentation but didn't find anything very useful there (maybe I didn't look hard enough).

Any code snippet that would give warning free (multiple bits) clock domain crossing would also be appreciated.

/Jussi