Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThis is very strange. I have a data bus from registers in domain clk250Mhz. Then I perform some logic function on the bus (combinational logic). The output processed bus is then entered to a synchronization chain clocked by the other clock clk200MHz. I receive a setup violation !! It seems like the tool does not understand that the register chain is for synchronization !
Is this related to the missing constraint ?