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Altera_Forum
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18 years ago

switching Bidirectional I/Os in FPGA

Hi, My project requires switching of SDRAM control and data signals between two DSP processors. Well, both the processors have their own SDRAM controller and signals. The Cyclone II FPGA is use...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I still think you have a problem with the simulation. So is the simulated data bus undefined, or high-z?

You did not say which tool you use for simulation. Do you have a correct model for the Cyclone II output buffer? If you see no change in data output when you switch OE on and off, something is wrong with the model or the stimulus...

About burst accesses, no Altera controller that I know of uses burst access for SDR SDRAM.