switching Bidirectional I/Os in FPGA

Altera has an old reference design which can be modified to use a custom interface, here (http://www.altera.com/support/refdesigns/sys-sol/computing/ref-sdr-sram.html).

If you want to read more about SDRAM, just download a datasheet from a manufacturer, like micron (pdf) (http://download.micron.com/pdf/datasheets/dram/sdram/256msdram.pdf). Googling for "sdram state machine" returns some links with state diagrams, also.

Probably you will have to write your own glue logic to hook onto your DSP memory interface, which might not be exactly trivial if you intend to use the SDRAM as a boot memory.

You say the simulation returns wrong results, and the output are undefined. Can you give some details about your simulation setup, testbench and stimulus?