switching Bidirectional I/Os in FPGA

Thanks for the reply. Well, I've thought of that solution too.. SDRAM controller in FPGA. But am tryin to use less resources and improve the timings with existing setup. So am really looking at just switching the SDRAM signals between the processors. I've also tried a bidirectional switching of the data bus based on the CS# and WE# signals, but still the simulations dont show up correctly.

Moreover, the SDRAM controllers available from Altera and others have their own local side which does not match the processors local side which i use. I even tried modifying the SDRAM controller but not working out though!

If you got any SDR SDRAM core with a simple local side interface (Addr, Data, RD/Wr#, CS#, OE#) please share them. Else if you've got a design doc on SDR SDRAM controller that would suffice too. I searched the web for SDRAM controller documentation, but didnt get any good one which details the exact state machine.