Forum Discussion
Altera_Forum
Honored Contributor
18 years agoYes, you need to drive the output enable for the bidir pins properly. This requires an SDRAM controller (more or less) to be present in the FPGA.
Rather than relying on the SDRAM controllers in the DSPs, you would make things much easier by using a simpler memory interface, like asynchronous SRAM to transfer data to/from FPGA - and implement a state machine + SDRAM controller in the FPGA.