[SVA] signal rise and stay stable -> how to write an assertion?

Most FPGA engineers are happy writing immediate assertions (using assert statement without a property), but SVA is another thing, and comes under the verification topic. Most FPGA engineers are happy writing a testbench that gives them a waveform and/or writing a self checking testbench. These can be done without SVA/PSL. As the syntax is nothing like standard RTL, it is outside the comfort zone for most, and is often the preserve of verification engineers, or people that work on ASICs. Im not sure about Modelsim, But I know that the cheapest versions of ActiveHDL and Xilinx Xsim do not support SVA (XSim just ignores SVA, ActiveHDL needs a more expensive licence).