[SVA] signal rise and stay stable -> how to write an assertion?

The more complicated your assertion, the harder your simulator has to work on every cycle to check an assertion. If you have a multi cycle assertion, you could have several overlapping assertions, which just adds load to your cpu. And if you ever get into formal verification, your prove time will just explode, if the assertion works at all.

Ideally you want assertions that are as simple as possible, ideally a |-> b. If necessary, you should write auxiliary code to achieve this, rather than putting the code in the assertion.

My example can easily be adapted to check for property 2), possibly as a sequence with your first line in your example code.

For 3), you could just write.

Assert property (@(posedge clk) $rose(event2) |=> $fell(signal) )

I am not a regular user of sva. Sva is also something very few FPGA engineers will be using. You might get better answers at the mentor verification academy forum.