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Altera_Forum's avatar
Altera_Forum
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7 years ago

[SVA] signal rise and stay stable -> how to write an assertion?

Hi All, How can I write an assertion for a signal, which should rise within between 10 to 20 cycles and stay stable (HIGH) until the assertion will be disabled? Thank you!
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Best to write a counter to count the number of cycles signal is high, then assert the counter when the signal goes low. 


Int cnt;
Always @(posedge clk) begin
  If signal = 1'b0 cnt = 0;
  Else cnt = cnt + 1;
End;
Assert property ( @(posedge clk) $fell(sig) |-> (cnt >= 10 && cnt <= 20); )