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Honored Contributor
Honored Contributor[SVA] signal rise and stay stable -> how to write an assertion?
Hi All, How can I write an assertion for a signal, which should rise within between 10 to 20 cycles and stay stable (HIGH) until the assertion will be disabled? Thank you!
Altera_ForumHonored Contributor
Honored ContributorBest to write a counter to count the number of cycles signal is high, then assert the counter when the signal goes low.
Int cnt;
Always @(posedge clk) begin
If signal = 1'b0 cnt = 0;
Else cnt = cnt + 1;
End;
Assert property ( @(posedge clk) $fell(sig) |-> (cnt >= 10 && cnt <= 20); )
