Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Suppress Warnings like 14110

Eploring a new design, I find (among others) warnings like this : Warning (14110): No clock transition on "pcie_top_4x125:pci .... register due to stuck clock or clock enable" which I w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I see your point. Are you actively using Incremental Compilation? You can also dynamically remove parts of your design or account for missing modules by setting the corresponding hierarchy as a design partition with the Netlist Type to Empty. This would also eliminate many of those synthesis warnings.