Regardless of whether it's the same density or migration-compatible, you could just put together a TCL script to run, or come up with different revisions of the same project (and use the pull-down at the top of the screen to select which one to build before compiling). This would allow you to use common VHDL/Verilog source files for both projects, and then build which one you want.
There is a QPF file for an entire project, and then individual QSF files for each revision in that project. For argument's sake, say you have two revisions of your project:
myproject_144
myproject_240
The myproject_144.qsf file would contain all of the specific build information (pinout, device, etc.) for the 144-pin Cyclone. Then, myproject_240.qsf would contain all of the same info that targets the 240-pin Cyclone. If you create the revision when all of the source files (VHD, etc.) up-to-date, they will both share all of the common source. You just need to make sure that if you add common source files down the road, you add them to both revisions (one at a time).
To build, you just select your revision from the pull-down menu at the top of the Quartus window (select myproject_144 or myproject_240), and then hit the compile button, and you will have the proper build. To automate the building of both (run it and then let it go), you could paste this info into the TCL script window (or put it in it's own TCL script):
load_package flow
project_open -revision myproject_144 myproject_top
execute_flow -compile
project_close
project_open -revision myproject_240 myproject_top
execute_flow -compile
project_close
Assuming your top-level project is called "myproject_top", this set of commands will sequentially build the two projects. By necessity, I have 7 flavors of my current project (that each take ~20 minutes to build), so I can kick off a build and come back a few hours later to 7 .SOF files.
Hope this helps.