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THe problem comes as you are missing several signals from the sensitivity list, namely x,y, y1, N, middle. But theres a couple of other issues:
The values only get updated when rst_n is '1'. It starts as '1', but will imediatly goes to '0'.
You declared your own subtype called unsigned. This is a bad idea, as numeric_std and std_logic_arith also declare unsigned types. You're going to have problems if you stick with these. I suggest deleting your custom unsigned subtype and the non-standard std_logic_arith library.
Also: I assume you know this code is not synthesisable (ie. You cannot put it on an FPGA) - I guess this is some kind of simulation model?
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Hi ,
Yes this is only a simulation model.
i simply specify y1<=integer(x-y ) where all are declared as integer .Though x and y hold there corresponding values say 231 and 6, y1 displays only its maximum range i.e -214748368.
And when i remove the subtype declaration it says unsigned is not directly visible.
Thanks in advance!
Honored Contributor
