Honored Contributor
Honored ContributorTHe problem comes as you are missing several signals from the sensitivity list, namely x,y, y1, N, middle. But theres a couple of other issues:
The values only get updated when rst_n is '1'. It starts as '1', but will imediatly goes to '0'. You declared your own subtype called unsigned. This is a bad idea, as numeric_std and std_logic_arith also declare unsigned types. You're going to have problems if you stick with these. I suggest deleting your custom unsigned subtype and the non-standard std_logic_arith library. Also: I assume you know this code is not synthesisable (ie. You cannot put it on an FPGA) - I guess this is some kind of simulation model?
