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zayjanos's avatar
zayjanos
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Struct type multi-bit port optimized to 1-bit port during mapping

Hello, I am using Quartus Lite 18.1. My RTL includes packed struct type ports, e.g.: input dll_steer_payld_t rx_rts_steer_info; The type definition for dll_steer_payld_t: typedef struct ...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    The code is fine. It's just this feature only supported in pro version without warning (check image):

    Same warnings also appear in standard version (check image):

    The synthesis engine of pro version is different compared with standard/lite synthesis engine.

    Thanks,

    Best regards,

    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

For the posted code example, I see only an inappropriate warning in the mapper report. As the technology map viewer clarifies, the pins are connected correctly. I don't see the claimed relation to synthesis engine capabilities. Besides unsubstantiated warnings, do you see any problems in actual design mapping, may be for a less trivial design?

I also don't understand the relation to Quartus Pro. There's effectively no choice between Quartus Standard versus Quartus Pro. Some devices need Quartus Pro, for others Quartus Pro isn't provided, e.g. Cyclone V used by the OP, even if you have the license. I know that Quartus Pro has more support for some new VHDL and SV features.