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zayjanos's avatar
zayjanos
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Struct type multi-bit port optimized to 1-bit port during mapping

Hello, I am using Quartus Lite 18.1. My RTL includes packed struct type ports, e.g.: input dll_steer_payld_t rx_rts_steer_info; The type definition for dll_steer_payld_t: typedef struct ...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    The code is fine. It's just this feature only supported in pro version without warning (check image):

    Same warnings also appear in standard version (check image):

    The synthesis engine of pro version is different compared with standard/lite synthesis engine.

    Thanks,

    Best regards,

    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

The code is fine. It's just this feature only supported in pro version without warning (check image):

Same warnings also appear in standard version (check image):

The synthesis engine of pro version is different compared with standard/lite synthesis engine.

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

zayjanos's avatar
zayjanos
Icon for New Contributor rankNew Contributor
3 years ago

Hi Sheng,

can you please confirm that the netlist created by Quartus Lite/Standard will not be logically equivalent with RTL because of this limitation of the synthesis engine?
This is just a warning in the map report, but it could be a critical warning or error because the functionality of the circuit is modified by connecting the struct type ports to GND.
My understanding is that I need to remove struct type ports from the RTL or switch to Quartus Pro to have logically equivalent netlist.

Thanks,
János