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zayjanos's avatar
zayjanos
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Struct type multi-bit port optimized to 1-bit port during mapping

Hello, I am using Quartus Lite 18.1. My RTL includes packed struct type ports, e.g.: input dll_steer_payld_t rx_rts_steer_info; The type definition for dll_steer_payld_t: typedef struct ...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    The code is fine. It's just this feature only supported in pro version without warning (check image):

    Same warnings also appear in standard version (check image):

    The synthesis engine of pro version is different compared with standard/lite synthesis engine.

    Thanks,

    Best regards,

    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

It depends on how you have the signal connected in your design. Can you show what this input is being connected to and confirm that bits aren’t getting optimized away?

zayjanos's avatar
zayjanos
Icon for New Contributor rankNew Contributor
3 years ago

These signals should not be optimized. I am afraid the tool cannot handle struct type ports.

Please find a simple example attached. You can load the .qpf file in Quartus and run "Compile Design".

Also attached the map.rpt file that includes the mentioned warnings:

; din ; Input ; Warning ; Input port expression (0 bits) is smaller than the input port (2 bits) it drives. Extra input bit(s) "din[1..0]" will be connected to GND. ;
; dout ; Output ; Warning ; Output or bidir port (2 bits) is wider than the port expression (0 bits) it drives; bit(s) "dout[1..0]" have no fanouts ;